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dual output, 6a/phase, highly integrated sup ir buck ? single-input voltage, synchronous buck regulator ir3892 1 www.irf.com ? 2013 international rectifier august 02, 2013 features ? single 5v to 21v application ? wide input voltage range from 1v to 21v with external vcc ? output voltage range: 0.5v to 0.86*pvin ? dual output, 6a/phase ? enhanced line/load regulation with feed- forward ? programmable switching frequency up to 1.0mhz ? internal digital soft-start ? enable input with voltage monitoring capability ? thermally compensated current limit and hiccup mode over current protection ? external synchronization with smooth clocking ? precision reference voltage (0.5v +/-1%) ? seq pin for sequencing applications ? integrated mosfets, drivers and bootstrap diode ? thermal shut down ? open feedback line protection ? over voltage protection ? interleaved phases to reduce input capacitors ? monotonic start-up ? operating junction temp: -40 o c ir3892 2 www.irf.com ? 2013 international rectifier august 02, 2013 basic application figure 1: ir3892 basic application circuit ? figure 2: efficiency [vin=12v, fsw=600khz] pin diagram 5mm x 6mm power qfn top view 25 pgnd1 12345 6789 13 12 11 10 17 16 15 14 18 boot2 pgood2 comp2 fb2 pgnd2 pgnd2 pvin2 pvin2 pgnd2 19 sw2 20 21 sw1 22 24 pgnd1 23 pgnd1 28 boot1 27 pvin1 26 pvin1 31 fb1 30 comp1 29 pgood1
ir3892 3 www.irf.com ? 2013 international rectifier august 02, 2013 functional block diagram gate drive logic gnd comp seq* fb en vref e/a intl_ss fb fault control logic rff vin soft start ssok fault por vref + - pgood rt/sync vsns uven uven por por uvlo vref uv/ ov/olfp fb uv/ ov/olfp hdin ldin oc over current protection thermal shutdown por tsd ov/oflp oc + - v ldo_ref + - ldo vcc ldrv hdrv fault control fault pgnd sw pvin boot vin vcc/ldo_out uvlo uvlo + + + - vcc *the seq pin is only available for channel 2 figure 3: ir3892 simplified block diagram (one phase)
ir3892 4 www.irf.com ? 2013 international rectifier august 02, 2013 pin descriptions pin # pin name pin description 1, 9 vsns 1/2 sense pins for over-voltage protection and pgood. a resistor divider with the same ratio as the respective feedback resistor divider should be connected between each vsns pin and its respective vout. 2, 8 en 1/2 enable pins for turning on and off the regulator. 3 vin input voltage for internal ldo. a 1.0f capacitor should be connected between this pin and pgnd. if external supply is connected to vcc pin, this pin should be shorted to vcc pin. 4 vcc/ldo_out input bias voltage, output of the in ternal ldo. place a minimum 2.2f cap from this pin to pgnd. 5 gnd signal ground for internal reference and control circuitry. 6 seq input to error amplifier for sequencing purposes. can be left floating for non-sequencing applications. it is only connected to the error-amplifier of channel 2. 7 rt/sync multi-function pin to set switching frequency. use an external resistor from this pin to gnd to set the free-running switching frequency. or use an external clock signal to connect to this pin through a diode, the device?s switching frequency is synchr onized with the external clock. 10, 31 fb 2/1 inverting inputs to the error amplifie rs. these pins are connected directly to the outputs of the regulator via resistor dividers to set the output voltages and provide feedback to the error amplifiers. 11, 30 comp 2/1 output of the error amplifiers. exte rnal resistor and capacitor networks are typically connected from these pins to its respective fb pin to provide loop compensation. 12, 29 pgood 2/1 power good status pins are open drai n outputs. the pins are typically connected to vcc via pull up resistors. 13, 28 boot 2/1 supply voltages for high side drivers, 100nf capacitors should be connected between these pins and their respective sw pin. 14, 15, 26, 27 pvin 2/1 input voltage for power stage. 16, 17, 18, 23, 24, 25 pgnd 2/1 power ground. these pins serv e as a separated ground for the mosfet drivers and should be connected to the system?s power ground plane. 19, 20, 21, 22 sw 2/1 switch nodes. these pins ar e connected to the output inductors.
ir3892 5 www.irf.com ? 2013 international rectifier august 02, 2013 absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only and functional operat ion of the device at these or any other conditions beyond those indicated in the operational sections of the spec ifications are not implied. pvin -0.3v to 25v vin -0.3v to 25v vcc -0.3v to 8v (note 1) sw -0.3v to 25v (dc), -4v to 25v (ac, 100ns) boot -0.3v to 33v boot to sw -0.3v to vcc + 0.3v (note 2) en, pgood -0.3v to vcc + 0.3v (note 2) other input/output pins -0.3v to 3.9v pgnd to gnd -0.3v to + 0.3v junction temperature range -40c to 150c storage temperature range -55c to 150c esd machine model class a human body model class 1c charged device model class iii moisture sensitivity level jedec level 2 @ 260c rohs compliant yes note: 1. vcc must not exceed 7.5v for junc tion temperature between -10c and -40c. 2. must not exceed 8v. thermal information thermal resistance, junction to case top ( jc_top ) 36 c/w thermal resistance, junction to pcb ( jb ) 3.6 c/w thermal resistance, junction to ambient ( ja ) (note 3) 24.7 c/w note: 3. thermal resistance ( ja ) is measured with components mounted on a high effective thermal conductivity test board in free air.
ir3892 6 www.irf.com ? 2013 international rectifier august 02, 2013 electrical specifications recommended operating conditions symbol definition min max unit pvin input bus voltage * 1.0 21 v vin supply voltage 5.0 21 vcc supply voltage ** 4.5 7.5 boot to sw supply voltage 4.5 7.5 v o output voltage 0.5 0.86 * pvin i o output current 0 6 a / phase fs switching frequency 300 1000 khz t j junction temperature -40 125 c * sw1/2 node must not exceed 25v ** when vcc is connected to an externally regulated supply, also connect vin. electrical characteristics unless otherwise specified, these specificatio ns apply over, 6.8v < vin=pvin < 21v in 0c < t j < 125c. typical values are specified at t a = 25c. parameter symbol conditions min typ max unit power stage power losses p loss vin = 12v, vout 1 = 1.8v, vout 2 = 1.2v, i o = 6a/phase, fs = 600khz, l1 =1.0uh, l2=1.0uh, note 4 2.72 w top switch r ds(on)_top vboot - vsw= 5.5v, i o = 4a, tj = 25c 27.5 36.4 m ? bottom switch r ds(on)_bot vcc = 5.5v, i o = 4a, tj = 25c 19.5 24.2 bootstrap diode forward voltage i(boot) = 10ma 300 450 mv sw leakage current i sw sw = 0v, enable = 0v 1 a sw = 0v, enable = high, vseq = 0v 2 a dead band time t db note 4 10 20 30 ns supply current vin supply current (standby) i in(standby) en = low, no switching 100 175 a vin supply current (dynamic) i in(dyn) en = high, fs = 600khz, 12.0 17 ma vcc ldo output output voltage v cc vin(min) = 6.8v, io = 0- 60ma, cload = 2.2uf 5 5.3 5.6 v vcc dropout v cc_drop icc = 60ma, cload = 2.2uf 0.75 v short circuit current ishort 120 ma
ir3892 7 www.irf.com ? 2013 international rectifier august 02, 2013 parameter symbol conditions min typ max unit oscillator rt voltage vrt 1.0 v frequency range f s rt = 80.6k 270 300 330 khz rt = 39.2k 540 600 660 rt = 23.2k, note 4 900 1000 1100 ramp amplitude vramp vin = 6.8v, vin slew rate max = 1v/ s, note 4 1.02 vp-p vin = 12v, vin slew rate max = 1v/ s, note 4 1.80 vin = 21v, vin slew rate max = 1v/ s, note 4 3.15 vcc=vin = 5v, for external vcc operation, note 4 0.75 min pulse width tmin(ctrl) note 4 60 ns max duty cycle dmax fs = 300khz, vin=pvin=12v 86 % fixed off time toff note 4 200 250 ns sync frequency range fsync 270 1100 khz sync pulse duration tsync 100 200 ns sync level threshold high 3 v low 0.6 error amplifier seq input offset voltage vos_vseq vseq ? vfb; vseq=250mv -3 +3 % input bias current ifb(e/a) -200 +200 na seq input impedance rin_seq(e/a) internal seq pull-up resistor 300 k ? sink current isink(e/a) 0.4 0.85 1.2 ma source current isource(e/a) 3 4 7 ma slew rate sr note 4 7 12 20 v/s gain-bandwidth product gbwp note 4 20 30 40 mhz dc gain gain note 4 80 90 110 db maximum voltage vmax(e/a) 1.7 2 2.3 v minimum voltage vmin(e/a) 120 220 mv vseq common mode voltage 0 0.77 v
ir3892 8 www.irf.com ? 2013 international rectifier august 02, 2013 parameter symbol conditions min typ max unit reference voltage feedback voltage vfb vseq=3.3v 0.5 v accuracy 0c < tj < 85c -1 +1 % -40c < tj < 125c, note 5 -1.5 +1.5 soft start soft start ramp rate ramp (ss_start) 0.14 0.18 0.22 mv / s fault protecion current limit i cc vcc=5.5v, tj = 25c 7.8 9 10.4 a / phase hiccup blanking time tblk_hiccup note 4 20.48 ms oflp trip threshold oflp(thresho ld) fb falling 65 70 75 %vref oflp fault prop delay oflp(delay) 0.1 0.3 0.5 s ovp trip threshold ovp(threshold) vsns rising 115 120 125 %vref ovp trip threshold hysteresis ovp_hys vsns falling from above 120% of vref, sync_fet turns off afterwards 25 mv ovp comparator delay ovp(delay) 2 s thermal shutdown note 4 140 c thermal hysteresis note 4 20 c v cc -start-threshold vcc_uvlo_start v cc rising trip level 4.0 4.2 4.4 v v cc -stop-threshold vcc_uvlo_stop v cc falling trip level 3.7 3.9 4.1 input / output signals enable-start-threshold en_uvlo_start supply ramping up 1.14 1.2 1.26 v enable-stop-threshold en_uvlo_stop supply ramping down 0.95 1 1.05 enable leakage current i en enable=3.3v 3 4.5 a power good upper threshold vpg(upper) vsns rising 80 85 90 %vref power good lower threshold vpg(lower) vsns falling 75 80 85 %vref lower threshold delay vpg(lower)_ dly vsns rising 1 1.3 1.6 ms pgood voltage low pg(voltage) i pgood = -5ma 0.5 v note: 4. guaranteed by design but not tested in production. 5. cold temperature performance is guaranteed via correl ation using statistical quality control. not tested in production.
ir3892 9 www.irf.com ? 2013 international rectifier august 02, 2013 typical efficiency and power loss curves pvin = 12v, vcc = internal ldo, io=0-6a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also consider ed in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages in the efficiency measurement while running a single channel and disabling the other. vout (v) lout (uh) p/n dcr (m ? ) 1.0 0.82 spm6550t-r82m (tdk) 4.2 1.2 1.0 SPM6550T-1R0M100A (tdk) 4.7 1.8 1.0 SPM6550T-1R0M100A (tdk) 4.7 3.3 2.2 7443340220 (wurth electronik) 4.4 5.0 2.2 7443340220 (wurth electronik) 4.4 ? ?
ir3892 10 www.irf.com ? 2013 international rectifier august 02, 2013 typical efficiency and power loss curves pvin = 12v, vin = vcc = 5v, io=0-6a, fs= 600khz, room temp erature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages in the efficiency measurement while running a single channel and disabling the other. vout (v) lout (uh) p/n dcr (m ? ) 1.0 0.82 spm6550t-r82m (tdk) 4.2 1.2 1.0 SPM6550T-1R0M100A (tdk) 4.7 1.8 1.0 SPM6550T-1R0M100A (tdk) 4.7 3.3 2.2 7443340220 (wurth electronik) 4.4 5.0 2.2 7443340220 (wurth electronik) 4.4 ? ?
ir3892 11 www.irf.com ? 2013 international rectifier august 02, 2013 typical efficiency and power loss curves pvin = 5v, vcc = 5v, io=0-6a, fs = 600khz, room temper ature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages in the efficiency measurement while running a single channel and disabling the other. vout (v) lout (uh) p/n dcr (m ? ) 1.0 0.68 pcmb065t-r65ms (cyntec) 3.9 1.2 0.82 spm6550t-r82m (tdk) 4.2 1.8 0.82 spm6550t-r82m (tdk) 4.2 3.3 1.0 SPM6550T-1R0M100A (tdk) 4.7 74 76 78 80 82 84 86 88 90 92 94 96 98 0123456 efficiency (%) iout(a) 1.0vout 1.2vout 1.8vout 3.3 vout ? ? 0.0 0.5 1.0 1.5 2.0 0123456 p ow e r lo ss (w ) iout(a) 1.0vout 1.2vout 1.8vout 3.3 vout
ir3892 12 www.irf.com ? 2013 international rectifier august 02, 2013 mosfet rdson variation over temperature
ir3892 13 www.irf.com ? 2013 international rectifier august 02, 2013 typical operating characteristics (-40c to +125c)
ir3892 14 www.irf.com ? 2013 international rectifier august 02, 2013
ir3892 15 www.irf.com ? 2013 international rectifier august 02, 2013 ?
ir3892 16 www.irf.com ? 2013 international rectifier august 02, 2013 theory of operation description the ir3892 uses a pwm voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. the switching frequency is programmable from 300khz to 1.0mhz and provides the capability of optimizing the design in terms of size and performance. ir3892 provides precisely regulated output voltage programmed via two external resistors from 0.5v to 0.86*pvin. the ir3892 operates with an internal low drop out regulator (ldo) which is connected to the vcc pin. this allows operation with a single supply. when using the internal ldo supply, the vin pin should be connected the pvin pin. if an external bias is used, it should be connected to the vcc pin and the vin pin should be shorted to the vcc pin. the device utilizes the on-resi stance of the low side mosfet (sync fet) as a current sense element. this method enhances the converter?s efficiency and reduces cost by eliminating the need for an external current sense resistor. ir3892 includes two low rds(on) mosfets using ir?s hexfet technology. these are specifically designed for high efficiency applications. under-voltage lockout and por the under-voltage lockout circ uits monitor the voltage on the vcc pin and the en1/2 pins. they ensure that the mosfet driver outputs remain in the off state whenever either of these signals drops below the set thresholds. normal operation resumes once vcc and en rise above their thresholds. the por (power on ready) signal is high when all these signals reach the valid logic level (see system block diagram). enable the en pin offers another leve l of flexibility for startup. each channel of the ir3892 is controlled by a separate en pin. when the voltage at an en pin voltage exceeds its precise threshold (en_uvlo_start), the respective channel turns on. the precise threshold allows the user to implement an under-voltage lockout (uvlo) function. by deriving the en pin voltage from the bus voltage (pvin) through a suitable resistor divider, the user can set a pvin threshold voltage. the resistor divider scales the pvin voltage for the en pin. only after the bus voltage reaches or exceeds this level will the voltage at the enable pin exceeds its threshold and enable the respective ir3892 channel. by connecting ir3892 in this configuration, the user can enable the part by applying pvin and ensures the ir3892 does not turn on until the bus voltage reaches the desired level (figure 4). therefore, in addition to being a logic input pin that enables channels on ir3892, the en pin also offers uvlo functionality. uvlo functionality is particularly desirable for high output voltage applications, where it is beneficial to disable the ir3892 until pvin exceeds the desired output voltage level. figure 4: normal startup: ir3892 channel starts when pvin reaches 10.2v by connecting en to pvin using a resistor divider.
ir3892 17 www.irf.com ? 2013 international rectifier august 02, 2013 vcc pvin=vin intl_ss 1/2 en1/2 > 1.2v vo 1/2 figure 5: recommended startup for normal operation vcc pvin=vin intl_ss 2 en2 > 1.2v intl_ss 1 en1 > 1.2v vo1 vo2 figure 6: recommended startup for sequencing operation (ratiometric or simultaneous) figure 5 shows the recommended start-up sequence for the normal (non-sequenci ng) operation of ir3892, when en pins are used as a logic input. figure 6 shows the recommended startup sequence for sequenced operation of ir3892. pre-bias startup ir3892 begins each start up by pre-charging the output to prevent oscillation and disturbances to the output voltage. the buck converter starts in an asynchronous fashion a nd keeps the synchronous mosfet (sync fet) off until the first gate signal for control mosfet (ctrl fet) is generated. figure 7 shows a typical pre-bias sequence. the sync fet always starts with a narrow pulse width (12.5% of the switching period). the pulse width increase after 16 pulses by 12.5% until the out put reaches steady state value. there are 16 pulses for each step. figure 8 shows the series of 16 x 8 startup pulses. figure 7: pre-bias start up ... ... ... hdrv ... ... ... 16 end of pb ldrv 12.5% 25% 87.5% 16 ... ... ... ... figure 8: pre-bias startup pulses soft-start ir3892 has an internal digital soft-start to control the output voltage rise and to limit the current surge during start-up. to ensure the correct start-up, the soft-start sequence initiates when the en and vcc rise above their uvlo thresholds and generates power on ready (por) signal. the internal soft-start rises with the typical rate of 0.2mv/s from 0v to 1.5v. figure 9 shows the waveforms during soft-start. the normal vout start-up time is fixed, and is equal to: ? ? ms s mv v v tstart 7 . 2 / 18 . 0 15 . 0 65 . 0 ? ? ? ? (1) during the soft-start the over-current protection (ocp) and the over-voltage protection (ovp) is enabled to protect the device from short circuit or over voltage events.
ir3892 18 www.irf.com ? 2013 international rectifier august 02, 2013 figure 9: theoretical operation waveforms during soft- start (non-sequencing) operating frequency the switching frequency can be programmed between 300khz-1.0mhz by connecting an external resistor from r t /sync pin to gnd. table 1 tabulates the oscillator frequency versus r t . table 1: switching frequency (fs) vs. external resistor (r t ) rt (k ? ) freq (khz) 80.6 300 60.4 400 48.7 500 39.2 600 34 700 29.4 800 26.1 900 23.2 1000 external synchronization ir3892 incorporates an internal phase lock loop (pll) circuit which enables synchronization of the internal oscillator to an external cl ock. this function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple point-of-load (pol) regulators are used. a multiple- function pin, rt/sync, is used to connect the external clock. if the external clock is present before the converter turns on, rt/sync pin can be connected to the external clock solely and no resistor is required. if the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free-running frequency, an external resistor from rt/sync pin to gnd is required to set the free running frequency. when an external clock is applied to rt/sync pin after the converter runs in steady state with its free-running frequency, a transition from the free-running frequency to the external clock frequency will happen. the switching frequency gradually synchronizes to the external clock frequency regardless of which one is faster. on the contrary, when the external clock signal is removed from rt/sync pin, the switching frequency gradually returns to the free-running frequency. in order to minimize the impact from these transitions to output voltage, a diode is recommended to add between the external clock and rt/sync pin. figure 10 shows the timing diagram of these transitions. sw sync ... ... gradually change fs1 fs2 fs1 free running frequency synchronize to the external clock return to free- running freq gradually change figure 10: timing diagram for synchronization to an external clock (fs1>fs2 or fs1 ir3892 19 www.irf.com ? 2013 international rectifier august 02, 2013 over current protection (current limit and hiccup mode) the over-current protection is performed by sensing current through the r ds(on) of the sync fet. this method enhances the converter?s efficiency and reduces cost by eliminating a current sense resistor. the current limit is pre-set internally and compensated to maintain an almost constant limit over temperature. ir3892 determines over-current events when the synchronous fet is on. ocp circuit samples this current for 40 nsec typically after the rising edge of the pwm set pulse which has a width of 12.5% of the switching period. the pwm pulse starts at the falling edge of the pwm set pulse. this makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. an oc condition is detected if the load current exceeds the threshold, the converter enters into hiccup mode. pgood will go low and the internal soft start signal will be pulled low. 2 i i i limit ocp ? ? ? (2) i ocp = dc current limit hiccup point i limit = current limit valley point ? i = inductor ripple current hiccup mode is when the converter stops and waits before restarting. the channel waits for tblk_hiccup, 2.48 ms typical, before the oc signal resets and restarts. in normal application, the converter restarts with a pre-bias sequence and soft-start. figure 11 shows the timing diagram of the above oc protection. if another oc event is detected, the part repeats hiccup mode. figure 11: timing diagram fo r pulse-by-pulse current limit and hiccup mode thermal shutdown ir3892 provides thermal protection. a thermal fault is detected, when the temperature of the part reaches the thermal shutdown thres hold, 145c typical. a thermal fault results in both channels turning off. the power mosfets are disabled during thermal shutdown. ir3892 automatically restarts when the temperature of the part drops back below the lower thermal limit, typically 20c below the thermal shutdown threshold. feed-forward feed-forward is an important feature which helps with stability and preserves load transient performance during pvin changes. in ir3892, feed-forward (f.f.) function is enabled when vin pin is connected to pvin pin and vin>5.0v. the pwm ramp amplitude (vramp) is proportionally changed with respect to vin to maintain pvin/vramp ratio. the ratio is almost constant throughout the vin range (as shown in figure 12). by maintaining a constant pvin/vramp, the control loop bandwidth and phase margin are more constant. f.f. function also helps minimize the effect of pvin changes on the output voltage. feed-forward is based on the vin voltage and needs to be accounted for when calculating ir3892 compensation. the pvin/vramp ratio is not maintained when vin and pvin are not equal. this is the case when an external bias voltage for vcc. when using an external vcc voltage, vin pin should be connected to the vcc pin instead of the pvin pin. compensation for the configuration should reflect the separation. figure 12: timing diagram for feed forward (f.f.) function
ir3892 20 www.irf.com ? 2013 international rectifier august 02, 2013 low dropout regulator (ldo) ir3892 has an integrated low dropout (ldo) regulator which can provide gate drive voltage for both drivers. when using an internally biased configuration, the ldo draws from the vin pin and provides a 5.3v (typ.), as shown in figure 13. vin and pvin can be connected together as shown in the internally biased single rail configuration, figure 14. an external bias configur ation can provide gate drive voltage for the drivers instead of the internal ldo. to use an external bias, connected to vin and vcc to the external bias, as shown in figure 15. pvin can also be connected or a different rail can be used. when using multiple rail configurations, calculate the compensation vramp associated with vin. vramp is derived from vin which can be different from pvin, refer to feed-forward section. figure 13: internally biased configuration figure 14: internally biased single rail configuration figure 15: externally biased configuration output voltage sequencing ir3892 can accommodate user sequencing options using seq, en1/2, and pgood1/2 pins. in the block diagram presented on page 3, the error-amplifier (e/a) has been depicted with three positive inputs. ideally, the input with the lowest vo ltage is used for regulating the output voltage and the other two inputs are ignored. in practice the voltages of the other two inputs should be at least 200mv greater than the referenced voltage input so that their effects can completely be ignored. in normal operating condition, the ir3892 channels initially follow their internal soft-starts (intl_ss) and then references vref. after enable goes high, intl_ss begins to ramp up from 0v. the fb pin follows the intl_ss until it approaches vref where the e/a starts to reference the vref instead of the intl_ss (refer to figure 16). vref and seq are not referenced initially because they are higher than intl_ss. vref is 0.5v, typical. seq is internally pulled up to approximately 3.3v when left floating in normal operation and only used by channel 2. in sequencing mode of operat ion, vout2 is initially regulated with the seq pin. vout2 ramps up similar to the normal operation, but intl_ss is replaced with seq. seq is kept to ground level until intl_ss signal reaches its final value. fb2 follows seq, until seq approaches vref where the e/a switches reference to the vref. vout2 is then regulated with respect to internal vref (refer to figure 17). the final seq voltage should between 0.7v and 3.3v.
ir3892 21 www.irf.com ? 2013 international rectifier august 02, 2013 fb/vsns 1.3 ms* pgood ovp is activated 0.65v * typical filter delay intl_ss vpg(upper) vpg(lower) ovp(threshold) ovp(hys) 1.3 ms* ldrv turned off figure 16: timing diagram for output sequence figure 17: timing diagram for sequence startup (seq ramping up/down) ir3892 can perform simultaneous or ratiometric sequencing operations. simultaneous sequencing is when the both outputs rise at the same rate. during ratiometric sequencing, the ratio of the two outputs is held constant during power-up. figure 19 shows examples of the two sequencing modes. ir3892 uses a single configuration to implement both mode of sequencing operations. figure 18 shows the typical circuit configuration for both modes of sequencing operation. the sequencing mode is determined by the r a /r b , r e /r f , and r c /r d ratios. if r e /r f = r c /r d , simultaneous startup is achieved. vout2 follows vout1 until the voltage at the seq pin reaches vref. after the voltage at the seq pin exceeds vref, vref dictates vout2. in ratiometric startup, vout2 rises at a slower rate than vout1. the resistor values are set up in the following way, r a /r b > r e /r f > r c /r d . table 2 summarizes the required conditions to achieve simultaneous or ratiometric sequencing operations. table 2: required conditions for simultaneous / ratiometric tracking and sequencing operating mode seq required condition normal (non-sequencing, non-tracking) floating D simultaneous sequencing ramp up from 0v r a /r b >r e /r f =r c /r d ratiometric sequencing ramp up from 0v r a /r b >r e /r f >r c /r d figure 18: application circuit for simultaneous and ratiometric sequencing
ir3892 22 www.irf.com ? 2013 international rectifier august 02, 2013 vcc vo1 (master) vo2 (slave) (a) vo1 (master) vo2 (slave) (b) intl_ss2 en1 en2 figure 19: typical waveforms for sequencing mode of operation: (a) simultaneous, (b) ratiometric over-voltage pr otection (ovp) over-voltage protection (ovp) disables the channel when the output voltage exceeds the over-voltage threshold. ir3892 achieves ovp by comparing vsns pin to the internal over-voltage threshold set at ovp(threshold), 1.2*vref typical. vsns voltage is determined by an external voltage divider resistor network connected to the output in typical application. when vsns exceeds the over-voltage threshold, an over-voltage is detected and ov signal asserts after ovp(delay). the high side drive signal hdrv is turned off immediately and pgood flags low. the low side drive signal is kept on until the vsns voltage drops below the lower threshold. after that, hdrv is latched off until a reset is performed by cycling either vcc or the respective en. vsns hdrv ldrv pgood ovp(threshold) ovp(hys) 2us * *typical filter delay figure 20: timing diagram for ovp open feedback-l oop protection open feedback loop protection (oflp) is devised to shutdown the channel in case the feedback is broken. oflp is activated when the vsns is above the vpg(upper) threshold, 0.85*vref typical, and remains active while vsns is above the vpg(lower) threshold, 0.80*vref. when fb drop below oflp(threshold) threshold, 0.70*vref, oflp disables switching and pulls down on pgood. the part remains disabled until fb rises above oflp(threshold) plus oflp(hys), 0.75*vref. this function does not latch the part off nor does it require an en or a vcc toggle to re-enable the part. figure 21: timing diagram for open feedback line protection (oflp) power good output pgood is an open drain pin that monitors the uv, fault and the por signals. pgood signal asserts approximately 1.3ms, after vsns rises above vgp(upper) threshold, 0.85*vref typical, while fault is low and por is high. it remains asserted while fault is low and por is high and vsns stays above vgp(lower) threshold, 0.80*vref typical. when vsns falls below vgp(lower) threshold there is a typical 2s delay before pg ood goes low. the two pgood signals are independent of each other and are set according to their respective channel. switch node phase shift the two converters on the ir3892 run interleaving phases by 180 to reduce input filter requirements. the two converters are synchronized to the user programmable oscillator. channel 1 runs in phase with the oscillator while channel 2 runs out of phase. staggering the switching cycles reduces the time the converters draw current from the supply simultaneously. the pulses of current drawn from the input induce voltage ripples ac ross the input capacitor. the voltage ripple shapes are dependent on the different loading and output voltages of the two converters. by switching t he converters at different times, the magnitude of voltage ripples reduces and input filter requirements become less stringent.
ir3892 23 www.irf.com ? 2013 international rectifier august 02, 2013 minimum on-time considerations the minimum on-time is the shortest amount of time which the control fet may be reliably turned on. internal delays and gate drive make up a large portion of the minimum on-time. ir3892 has a minimum on- time of 60ns. any design or application using ir3892 should operation with a pulse width greater than minimum on- time. this is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. s out s on f pvin v f d t ? ? ? (3) in any application that uses ir3892, the following condition must be satisfied: on on t t ? (min) (4) s in out on f pv v t ? ? (min) (5) (min) on out s in t v f pv ? ? ? (6) the minimum output voltage is limited by the reference voltage and hence vout(min) = 0.5v. for vout(min) = 0.5v, (min) on out s in t v f pv ? ? ? (7) s v ns v f pv s in ? / 33 . 8 60 5 . 0 ? ? ? ? therefore, with an input voltage 16v and minimum output voltage, the converter should be designed for switching frequency not to exceed 520khz. conversely, the input voltage (pvin) should not exceed 5.55v for operation at the maximum recommended operating frequency (1.0mhz) and minimum output voltage (0.5v). increasing the pvin greater than 5.55v will cause pulse skipping. maximum duty ratio maximum duty ratio is lower at higher frequencies and higher vin voltages. a maximum off-time of 250ns is specified for ir3892. this provides an upper limit on the operating duty ratio at any given switching frequency. the off-time becomes a larger percentage of the switching period when high switching frequencies are used. thus, a lower the maximum duty ratio can be achieved when frequencies increase. feed-forward from the vin voltage placed a limitation on the maximum duty cycle by saturating the compensation ramp. by maintaining a constant vin/vramp, the effective vramp voltage is increased while the maximum range is remains the same. the ramp reaches the maximum limit before reaching the expected level. reaching the maximum limit ends the switching cycle prematurely and results in a lower maximum duty cycle. maximum duty cycle is dependent on the vin and switching frequency. figure 22 is a theoretical plot of the maximum duty cycle vs. the switching frequency using typical parameter values. it shows how the maximum duty cycle is influenced by the vin and the switching frequency. figure 22: maximum duty cycle vs. switching frequency
ir3892 24 www.irf.com ? 2013 international rectifier august 02, 2013 design example the following example is a typical application for ir3892. the application circuit is shown in v in = p v in = 12v (21v max) f s = 600khz channel 1: v o = 1.8v i o = 6a ripple voltage = 1% * v o ? v o = 4% * vo (for 30% load transient) channel 2: v o = 1.2v i o = 6a ripple voltage = 1% * v o ? v o = 4% * vo (for 30% load transient) enabling the ir3892 as explained earlier, the precise threshold of the enable lends itself well to implementation of a uvlo for the bus voltage as shown in figure 23. figure 23: using enable pin for uvlo implementation for a typical enable threshold of v en = 1.2 v 2 . 1 2 1 2 (min) ? ? ? ? en in v r r r pv (8) en in en v pv v r r ? ? (min) 1 2 (9) for pv in (min) =9.2v, r 1 =49.9k and r 2 =7.5k ohm is a good choice. programming the frequency for f s = 600 khz, select r t = 39.2 k ? , using table 1. output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb pin is the inverting input of the error amplifier, which is internally referenced to vref. the divider ratio is set to equal vref at the fb pin when t he output is at its desired value. when an external resistor divider is connected to the output as shown in figure 24, the output voltage is defined by using the following equation: ? ? ? ? ? ? ? ? ? ? ? 6 5 1 r r v v ref o (10) ? ? ? ? ? ? ? ? ? ? ? ref o ref v v v r r 5 6 (11) for the calculated values of r5 and r6, see feedback compensation section. figure 24: typical application of the ir3892 for programming the output voltage bootstrap capacitor selection to drive the control fet, it is necessary to supply a gate voltage at least 4v great er than the voltage at the sw pin, which is connected to the source of the control fet. this is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (c1). the operation of the circuit is as follows: when the sync fet is turned on, the capacitor node connected to sw is pulled down to ground. the capacitor charges towards v cc through the internal bootstrap diode (figure 25), which has a forward voltage drop v d . the voltage v c across the bootstrap capacitor c1 is approximately given as: d cc c v v v ? ? (12)
ir3892 25 www.irf.com ? 2013 international rectifier august 02, 2013 when the control fet turns on in the next cycle, the capacitor node connected to sw rises to the bus voltage v in . however, if the value of c1 is appropriately chosen, the voltage v c across c1 remains approximately unchanged and the voltage at the boot pin becomes: d cc in boot v v v v ? ? ? (13) l vc c1 v in v cc sw + - boot pgnd + v d - ir3892 cvin figure 25: bootstrap circuit to generate vc voltage a bootstrap capacitor of value 0.1uf is suitable for most applications. input capacitor selection the ripple currents generated during the on time of the control fets should be provided by the input capacitor. the rms value of this ripple for each channel is expressed by: ?? d d i i o rms ? ? ? ? 1 (14) in o v v d ? (15) where: d is the duty cycle i rms is the rms value of the input capacitor current. io is the output current. for channel 1, i o =6a and d =0.15, the i rms = 2.14a. for channel 2, i o =6a and d =0.1, the i rms = 1.8a. ceramic capacitors are recommended due to their peak current ca pabilities. they al so feature low esr and esl at higher frequency which enables better efficiency. for this application, it is advisable to have 4x10uf, 25v ceramic capacitors, c3216x5r1e106k from tdk. in addition to these, although not mandatory, a 1x330uf, 25v smd capacitor eev- fk1e331p from panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. inductor selection inductors are selected based on output power, operating frequency and effi ciency requirements. a low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but may reduce efficiency and cause higher output noise. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( ? i ). the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: s o in f d t t i l v v 1 ; ? ? ? ? ? ? ? ? ?? s in o o in f i v v v v l ? ? ? ? ? ? (16) where: v in = maximum input voltage v 0 = output voltage ? i = inductor peak-to-peak ripple current f s = switching frequency ? t = on time for control fet d = duty cycle if ? i 30%* i o , then the channel 1 output inductor is calculated to be 1.42 h. select l =1.0 h, spm6550t- 1r0m100a, from tdk which provides a compact, low profile inductor suitable for this application. for channel 2, the output inductor is calculated to be 1.0 h. select l =1.0 h, SPM6550T-1R0M100A, from tdk. output capacitor selection the voltage ripple and transient requirements determine the output capacitors type and values. the criterion is normally based on the value of the
ir3892 26 www.irf.com ? 2013 international rectifier august 02, 2013 effective series resistance (esr). however the actual capacitance value and the equivalent series inductance (esl) are other co ntributing components. these components can be described as: ?? ?? ) ( c o esl o esr o o v v v v ? ? ? ? ? ? ? esr i v l esr ? ? ? ? ) ( 0 esl l v v v o in esl ? ? ? ? ? ? ? ? ? ? ) ( 0 s o l c f c i v ? ? ? ? ? 8 ) ( 0 (17) where: ? v 0 = output voltage ripple ? i l = inductor ripple current since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. the ir3892 can perform well with all types of capacitors. as a rule, the capacitor must have low enough esr to meet output ripple and load transient requirements. the goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. therefore it is advisable to select ceramic capacitors due to their low esr and esl and small size. four of tdk c2012x5r0j226m (22uf/0805/x5r/6.3v) capacitors is a good choice for channel 1 and channel 2. it is also recommended to use a 0.1f ceramic capacitor at the output for high frequency filtering. feedback compensation the ir3892 is a voltage mode controller. the control loop is a single voltage feedback path including error amplifier and error compar ator. to achieve fast transient response and accurate output regulation, a compensation circuit is necessary. the goal of the compensation network is to have a stable closed-loop transfer function with a high crossover frequency and phase margin greater than 45 o . the output lc filter introduces a double pole, - 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o . the resonant frequency of the lc filter is expressed as follows: o o lc c l f ? ? ? ? ? 2 1 (18) figure 26 shows gain and phase of the lc filter. since we already have 180 o phase shift from the output filter alone, the system runs the risk of being unstable. phase 0 0 f lc 0 frequency f lc frequency 0 0 -180 0 0db -40db/decade -90 gain figure 26: gain and phase of lc filter the ir3892 uses a voltage-type error amplifier with high-gain and high-bandwidth. the output of the amplifier is available for dc gain control and ac phase compensation. the error amplifier can be compensated either in type ii or type iii compensation. local feedback with type ii compensation is shown in figure 27. this method requires that the output capacitor should have enough esr to satisfy stability requirements. if the output capacitor?s esr generates a zero at 5khz to 50khz, the zero generates acceptable phase margin and the type ii compensator can be used. the esr zero of the output capacitor is expressed as follows: o esr c esr f ? ? ? ? ? 2 1 (19)
ir3892 27 www.irf.com ? 2013 international rectifier august 02, 2013 v out v ref r6 r5 c pole c3 r3 ve f z f pole e/a z f frequency gain(db) h(s) db fb comp z in figure 27: type ii compensation network and its asymptotic gain plot the transfer function ( v e /v out ) is given by: 3 5 3 3 1 ) ( c sr c sr z z s h v v in f out e ? ? ? ? ? ? (20) the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: 5 3 ) ( r r s h ? (21) 3 3 2 1 c r f z ? ? ? ? ? (22) first select the desired zero-crossover frequency ( f o ): esr o f f ? and s o f f ? ? ) 10 / 1 ~ 5 / 1 ( (23) use the following equation to calculate r3: 2 5 3 lc in esr o ramp f v r f f v r ? ? ? ? ? (24) where: v in = maximum input voltage v osc = amplitude of the oscillator ramp voltage f o = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 5 = feedback resistor to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: lc z f f ? ? % 75 o o z c l f ? ? ? ? ? 2 1 75 . 0 (25) use equation (22), (23) and (24) to calculate c3. one more capacitor is sometimes added in parallel with c3 and r3. this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: pole pole p c c c c f ? ? ? ? ? 3 3 2 1 ? (26) the pole sets to one half of the switching frequency which results in the capacitor c pole : s s pole f r c f r c ? ? ? ? ? ? ? 3 3 3 1 1 1 ? ? (27) for an unconditional stability general solution using any type of output capacito rs with a wide range of esr values, use local feedback with type iii compensation network. type iii compensation network is typically used for voltage-mode controller as shown in figure 28.
ir3892 28 www.irf.com ? 2013 international rectifier august 02, 2013 v out v ref r6 r5 r4 c4 c2 c3 r3 ve f z 1 f z 2 f p 2 f p 3 e / a z f z in frequency gain (db) |h(s)| db fb comp figure 28: type iii compensation network and its asymptotic gain plot again, the transfer function is given by: in f out e z z s h v v ? ? ? ) ( by replacing z in and z f , according to figure 28, the transfer function can be expressed as: ???? ?? ?? ?? 4 4 3 2 3 2 3 3 2 5 5 4 4 3 3 1 1 1 1 ) ( c sr c c c c sr c c sr r r sc c sr s h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (28) the compensation network has three poles and two zeros and they are expressed as follows: 0 1 ? p f (29) 4 4 2 2 1 c r f p ? ? ? ? (30) 2 3 3 2 3 2 3 3 2 1 2 1 c r c c c c r f p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (31) 3 3 1 2 1 c r f z ? ? ? ? (32) ?? 5 4 5 3 4 2 2 1 2 1 r c r r c f z ? ? ? ? ? ? ? ? ? (33) cross over frequency is expressed as: o o ramp in o c l v v c r f ? ? ? ? ? ? ? 2 1 4 3 (34) based on the frequency of the zero generated by the output capacitor and its esr, relative to the crossover frequency, the compensation type can be different. table 3 shows the compensation types for relative locations of the crossover frequency. table 3: different types of compensators compensator type f esr vs f o typical output capacitor type ii f lc < f esr < f o < f s /2 electrolytic type iii f lc < f o < f esr sp cap, ceramic the higher the crossover frequency is, the potentially faster the load transient re sponse will be. however, the crossover frequency should be low enough to allow attenuation of switching noise. typically, the control loop bandwidth or crossover frequency ( f o ) is selected such that: ? ? s o f f * 1/10 ~ 1/5 ? the dc gain should be large enough to provide high dc-regulation accuracy. the phase margin should be greater than 45 o for overall stability. the specifications for designing channel 1: v in = 12v v o = 1.8v v ramp = 1.8v (this is a function of vin, pls. see feed-forward section) v ref = 0.5v l o = 1.0uh c o = 4x22uf, esr 3m ? each it must be noted here that the value of the capacitance used in the compensator design must be
ir3892 29 www.irf.com ? 2013 international rectifier august 02, 2013 the small signal value. for instance, the small signal capacitance of the 22uf capacitor used in this design is 15uf at 1.8 v dc bias and 600 khz frequency. it is this value that must be used for all computations related to the compensation. the small signal value may be obtained from the manufacturer?s datasheets, design tools or spice models. alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency f lc and using equation (18) to compute the small signal c o . these result to: f lc = 20.6 khz f esr = 3.54 mhz f s /2 = 300 khz select crossover frequency f 0 =100 khz since f lc ir3892 30 www.irf.com ? 2013 international rectifier august 02, 2013 ?? 11 12 11 2 . 1 _ rsns rsns rsns vref vout ovp ? ? ? ? (36) vout_ ovp = 2.16 v selecting power good pull-up resistor the pgood1 and pgood2 are open drain outputs and require pull up resistors to vcc. the value of the pull- up resistors should limit the current flowing into the each pgood pin to be less than 5ma. a typical value used is 49.9k ? . the specifications for the channel 2 design: v in =12v v o =1.2v v ramp =1.8v (this is a function of vin, pls. see feed forward section) v ref =0.5v l o =1.0uh c o =4x22uf, esr 3m ? each in the calculations, 18uf is used for the 22uf c o capacitors due to the 1.2v bias and 600 khz frequency. these result to: f lc = 18.8 khz f esr = 2.95 mhz f s /2 = 300 khz select crossover frequency f 0 =100 khz since f lc ir3892 31 www.irf.com ? 2013 international rectifier august 02, 2013 21 1 85 . 0 22 ) _ ( rsns vref v rsns th pgood out ? ? ? ? ? ? ? ? ? ? ? ? (37) rsns22 = 11.83 k ? ; select 11.8 k ? , the typical over-voltage threshold is calculated below for channel 2. with above values for rsns22 and rsns21, ovp trip point (vout_ ovp ) is ?? 22 22 21 2 . 1 _ r sns rsns rsns vref vout ovp ? ? ? ? (38) vout_ ovp = 1.44 v
ir3892 32 www.irf.com ? 2013 international rectifier august 02, 2013 application diagram internally biased single rail gnd pgnd1/2 rt/sync seq pvin1/2 vin vcc figure 29: application circuit for 12v to 1.8v and 1.2v , 6a point of load converter using the internal ldo
ir3892 33 www.irf.com ? 2013 international rectifier august 02, 2013 suggested bill of materi al for application circuit 12v to 1.8v and 1.2v part reference qty value description manufacturer part number cpvin1 1 330uf smd, electrolytic , 25v, 20% panasonic eev-fk1e331p cpvin2 4 10uf 1206, 25v, x5r, 10% tdk c3216x5r1e106m cvin 1 1.0uf 0603, 25v, x5r, 10% murata grm188r61e105ka12d cvcc 1 2.2uf 0603, 16v, x5r, 20% tdk c1608x5r1c225m co1 co2 cboot1 cboot2 cpvin3 6 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104ka01d cc11 cc21 2 1000pf 0603, 50v, x7r, 10% murata grm188r71h102ka01d cc12 1 4.7nf 0603, 50v, x7r, 10% murata grm188r71h472ka01d cc13 1 100pf 0603, 50v, npo, 5% murata grm1885c1h101ja01d cc22 1 3.6nf 0603, 50v, npo, 5% murata grm1885c1h362ja01d cc23 1 82pf 0603, 50v, npo, 5% murata grm1885c1h820ja01d cout1 cout2 8 22uf 0805, 6.3v x5r, 20% tdk c2012x5r0j226m l0 l1 2 1.0uh smt 6.5x7x5mm, dcr=4.7m ? tdk SPM6550T-1R0M100A rbd1 rbd2 2 20 thick film, 0603, 1/10w, 1% panasonic erj-3ekf20r0v ren12 ren22 rpg1 rpg2 4 49.9k thick film, 0603, 1/10 w, 1% panasonic erj-3ekf4992v ren11 ren21 2 7.5k thick film, 0603, 1/10w, 1% panasonic erj-3ekf7501v rc11 rc21 2 210 thick film, 0603, 1/ 10w, 1% panasonic erj-3ekf2100v rc12 1 5.62k thick film, 0603, 1/ 10w, 1% panasonic erj-3ekf5621v rc22 1 6.65k thick film, 0603, 1/ 10w, 1% panasonic erj-3ekf6651v rfb11 rsns11 2 4.53k thick film, 0603, 1/10w, 1% panasonic erj-3ekf4531v rfb12 rsns12 rfb22 rsns22 4 11.8k thick film, 0603, 1/10 w, 1% panasonic erj-3ekf1182v rfb21 rsns21 2 8.45k thick film, 0603, 1/10w, 1% panasonic erj-3ekf8451v rt 1 39.2k thick film, 0603, 1/ 10w, 1% panasonic erj-3ekf3922v u1 1 ir3892 pqfn 5x6mm international rectifier ir3892mpbf
ir3892 34 www.irf.com ? 2013 international rectifier august 02, 2013 externally biased dual rail ir3892 l0 gnd pgnd1/2 rt/sync seq sw1 comp1 fb1 vsns1 boot1 en1 pgood1 ren12 ren11 pgood2 en2 boot2 sw2 comp2 comp2 l1 vsns2 ren22 ren21 pvin1/2 vin vcc cpvin1 cvcc cpvin2 cpvin3 cvin rfb12 rc12 cc13 cc12 cc11 rc22 rfb22 rc21 cc21 cc22 cc23 cboot1 cboot2 0.1 uf 0.1 uf 49.9 k rpg2 2.2 uf 1 uf 49.9 k rpg1 2 x 0.1 uf 49.9 k 7.5 k 49.9 k 7.5 k 330 uf 4 x 10 uf 11.8 k rsns12 4.53 k rsns11 4 x 22 uf 10 nf 220 pf 2.43 k 210 1000 pf 11.8 k 4.53 k rfb11 rc11 39.2 k rt vo1 pvin pg2 pg1 1.0 uh 1.0 uh 11.8 k 8.45 k rfb21 4 x 22 uf vo2 rsns22 11.8 k rbd2 20 rsns21 8.45 k 210 1000 pf 180 pf 8.2 nf 2.94 k rbd1 20 cout1 0.1 uf co1 cout2 0.1 uf co2 vin figure 30: application circuit for a 12v to 1.8v and 1. 2v, 4a point of load converter using external 5v vcc
ir3892 35 www.irf.com ? 2013 international rectifier august 02, 2013 suggested bill of material for application circuit 12v to 1.8v and 1.2v using external 5v vcc part reference qty value description manufacturer part number cpvin1 1 330uf smd, electrolytic, 25v, 20% panasonic eev-fk1e331p cpvin2 4 10uf 1206, 25v, x5r, 10% tdk c3216x5r1e106m cvin 1 1.0uf 0603, 25v, x5r, 10% murata grm188r61e105ka12d cvcc 1 2.2uf 0603, 16v, x5r, 20% tdk c1608x5r1c225m cpvin3 cboot1 cboot2 co1 co2 6 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104ka01d cc11 cc21 2 1000pf 0603, 50v, x7r, 10% murata grm188r71h102ka01d cc12 1 10nf 0603, 50v, x7r, 10% murata grm188r71h103ka01d cc13 1 220pf 0603, 50v, npo, 5% murata grm1885c1h221ja01d cc22 1 8.2nf 0603, 50v, x7r, 10% murata grm188r71h822ka01d cc23 1 180pf 0603, 50v, npo, 5% murata grm1885c1h181ja01d cout1 cout2 8 22uf 0805, 6.3v x5r, 20% tdk c2012x5r0j226m l0 l1 2 1.0uh smt 6.5x7x5mm, dcr=4.7m ? tdk SPM6550T-1R0M100A rbd1 rbd2 2 20 thick film, 0603, 1/10w, 1% panasonic erj-3ekf20r0v rc11 rc21 2 210 thick film, 0603, 1/10w, 1% panasonic erj-3ekf2100v rc12 1 2.43k thick film, 0603, 1/10w, 1% panasonic erj-3ekf2431v rc22 1 2.94k thick film, 0603, 1/10w, 1% panasonic erj-3ekf2941v ren11 ren21 2 7.5k thick film, 0603, 1/10w, 1% panasonic erj-3ekf7501v ren12 ren22 rpg1 rpg2 4 49.9k thick film, 0603, 1/10w, 1% panasonic erj-3ekf4992v rfb11 rsns11 2 4.53k thick film, 0603, 1/10w, 1% panasonic erj-3ekf4531v rfb12 rsns12 rfb22 rsns22 4 11.8k thick film, 0603, 1/10w, 1% panasonic erj-3ekf1182v rfb21 rsns21 2 8.45k thick film, 0603, 1/10w, 1% panasonic erj-3ekf8451v rt 1 39.2k thick film, 0603, 1/10w, 1% panasonic erj-3ekf3922v u1 1 ir3892 pqfn 5x6mm international rectifier ir3892mpbf
ir3892 36 www.irf.com ? 2013 international rectifier august 02, 2013 externally biased single rail gnd pgnd1/2 rt/sync seq pvin1/2 vin vcc figure 31: application circuit for a 5v to 1.8v and 1.2v, 4a point of load converter
ir3892 37 www.irf.com ? 2013 international rectifier august 02, 2013 suggested bill of materi al for application circuit 5v to 1.8v and 1.2v part reference qty value description manufacturer part number cpvin1 1 330uf smd, electrolytic, 25v, 20% panasonic eev-fk1e331p cpvin2 8 10uf 1206, 25v, x5r, 10% tdk c3216x5r1e106m cvin 1 1.0uf 0603, 25v, x5r, 10% murata grm188r61e105ka12d cvcc 1 2.2uf 0603, 16v, x5r, 20% tdk c1608x5r1c225m cpvin3 cboot1 cboot2 co1 co2 6 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104ka01d cc11 cc21 2 1000pf 0603, 50v, x7r, 10% murata grm188r71h102ka01d cc12 cc22 2 3.9nf 0603, 50v, x7r, 10% murata grm188r71h392ka01d cc13 cc23 2 91pf 0603, 50v, npo, 5% murata grm1885c1h910ja01d cout1 cout2 8 22uf 0805, 6.3v x5r, 20% tdk c2012x5r0j226m l0 l1 2 1.0uh smt 6.5x7x5mm, dcr=4.7m ? tdk SPM6550T-1R0M100A rbd1 rbd2 2 20 thick film, 0603, 1/10w, 1% panasonic erj-3ekf20r0v rc11 rc21 2 210 thick film, 0603, 1/10w, 1% panasonic erj-3ekf2100v rc12 rc22 2 5.62k thick film, 0603, 1/10w, 1% panasonic erj-3ekf5621v ren11 ren21 2 21k thick film, 0603, 1/10w, 1% panasonic erj-3ekf2102v ren12 ren22 2 41.2k thick film, 0603, 1/10w, 1% panasonic erj-3ekf4122v rfb11 rsns11 2 4.53k thick film, 0603, 1/10w, 1% panasonic erj-3ekf4531v rfb12 rsns12 rfb22 rsns22 4 11.8k thick film, 0603, 1/10w, 1% panasonic erj-3ekf1182v rfb21 rsns21 2 8.45k thick film, 0603, 1/10w, 1% panasonic erj-3ekf8451v rpg1 rpg2 2 49.9k thick film, 0603, 1/10w, 1% panasonic erj-3ekf4992v rt 1 39.2k thick film, 0603, 1/10w, 1% panasonic erj-3ekf3922v u1 1 ir3892 pqfn 5x6mm international rectifier ir3892mpbf
ir3892 38 www.irf.com ? 2013 international rectifier august 02, 2013 typical operating waveforms vin=pvin=12v, vo1=1.8v, iout1=0-6a , vo2=1.2v, iout1=0-6a, fs=600khz, room temperature, no air flow figure 32: startup with full load ch1:vout1, ch2:vout 2, ch3:vin, ch4:vcc figure 33: pgood signals at startup with full load ch1:vout1, ch2:vout2, ch3:pgood1, ch4:pgood2 figure 34: channel 1 startup with pre-bias, 1.52v ch1:vout1, ch3:pgood1, ch4:enable1 figure 35: channel 2 startup with pre-bias, 1.05v ch2: vout2, ch2: pgood2 , ch4:enable2 figure 36: inductor switch nodes at full load ch1:sw1, ch2:sw2 figure 37: output voltage ripples at full load ch1:vout1, ch2:vout2
ir3892 39 www.irf.com ? 2013 international rectifier august 02, 2013 typical operating waveforms vin=pvin=12v, vo1=1.8v, iout1=0-6a , vo2=1.2v, iout1=0-6a, fs=600khz, room temperature, no air flow figure 38: vout1 transient response , 4.2a to 6a step at 2.5a/sec ch1:vout1, ch2=vo ut2, ch4:iout1
ir3892 40 www.irf.com ? 2013 international rectifier august 02, 2013 typical operating waveforms vin=pvin=12v, vo1=1.8v, iout1=0-6a , vo2=1.2v, iout1=0-6a, fs=600khz, room temperature, no air flow figure 39: vout2 transient response , 4.2a to 6a step at 2.5a/sec ch1:vout1, ch2=vo ut2, ch4:iout2
ir3892 41 www.irf.com ? 2013 international rectifier august 02, 2013 typical operating waveforms vin=pvin=12v, vo1=1.8v, iout1=0-6a , vo2=1.2v, iout1=0-6a, fs=600khz, room temperature, no air flow figure 40: ch1 bode plot with 6a load, ch2 disabled. fo = 96.3 khz, phase margin = 56.2 degrees figure 41: ch2 bode plot with 6a load, ch1 disabled. fo = 97 khz, phase margin = 54 degrees
ir3892 42 www.irf.com ? 2013 international rectifier august 02, 2013 layout recommendations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. make the connections for the power components on the top layer with wide, copper filled areas or polygons. in general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. the inductor, input capacitors, output capacitors and the ir3892 should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input capacitor directly at the pvin pin of ir3892. the feedback part of the system should be kept away from the inductor and other noise sources. the critical bypass component s such as capacitors for pvin and vcc should be close to their respective pins. it is important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. in a multilayer pcb use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. it is recommended to place all the compensation parts over the analog ground plane on top layer. the power qfn is a thermally enhanced package. based on thermal performance it is recommended to use at least a 4-layers pcb. to effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. figure 42a-d illustrates the implementation of the layout guidelines outlined above, on the irdc3892 4-layer demo board. figure 42a: irdc3892 demo board lay out considerations ? top layer - compensation parts should be placed as close as possible to the comp pins - sw node copper is kept only at the top layer to minimize the switching noise - single point connection between agnd & pgnd, should be placed near the part and kept away from noise sources pgnd pvin vout1 vout2 a gnd - ground path length between vin- and vout1- should be minimized with maximum copper - ground path length between vin- and vout2- should be minimized with maximum copper - bypass caps should be placed as close as possible to their
ir3892 43 www.irf.com ? 2013 international rectifier august 02, 2013 figure 42b: irdc3892 demo board layout considerations ? bottom layer figure 42c: irdc3892 demo board layout considerations ? mid layer 1 figure 42d: irdc3892 demo board layout considerations ? mid layer 2 feedback and vsns trace routing should be kept away from noise sources vin pgnd agnd pgnd pgnd
ir3892 44 www.irf.com ? 2013 international rectifier august 02, 2013 pcb metal and comp onent placement evaluations have shown that the best overall performance is achieved using the substrate/pcb layout as shown in following figures. pqfn devices should be placed to an accuracy of 0.050mm on both x and y axes. self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. for further information, please refer to ?supirbuck ? multi-chip module (mcm) power quad flat no-lead (pqfn) board mounting application note .? (an1132) figure 43: pcb pad sizes detail 1 (dimensions in mm) figure 44: pcb pad sizes detail 2 (dimensions in mm) figure 45: pcb metal pad spacing (dimensions in mm)
ir3892 45 www.irf.com ? 2013 international rectifier august 02, 2013 solder resist ? ir recommends that the larger power or land area pads are solder mask defined (smd). this allows the underlying copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. ? when using smd pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the solder mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in x & y). ? however, for the smaller signal type leads around the edge of the device, ir recommends that these are non solder mask defined or copper defined. ? when using nsmd pads, the solder resist window should be larger than the copper pad by at least 0.025mm on each edge, (i.e. 0.05mm in x & y), in order to accommodate any layer to layer misalignment. ? ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. figure 46: smd pad sizes detail 1 (dimensions in mm)
ir3892 46 www.irf.com ? 2013 international rectifier august 02, 2013 figure 47: smd pad sizes detail 2 (dimensions in mm) figure 48: smd pad spacing (dimensions in mm)
ir3892 47 www.irf.com ? 2013 international rectifier august 02, 2013 stencil design ? stencils for pqfn can be us ed with thicknesses of 0.100-0.250mm (0 .004-0.010"). stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitab le reductions, give the best results. ? ? evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. this design is for a stencil thickness of 0.127mm (0.005"). the reduction should be adjust ed for stencils of other thicknesses. ? figure 49: stencil pad sizes (dimensions in mm)
ir3892 48 www.irf.com ? 2013 international rectifier august 02, 2013 figure 50: stencil pad spacing detail 1 (dimensions in mm) figure 51: stencil pad spacing detail 2 (dimensions in mm)
ir3892 49 www.irf.com ? 2013 international rectifier august 02, 2013 marking information figure 52: marking information
ir3892 50 www.irf.com ? 2013 international rectifier august 02, 2013 packaging information
ir3892 51 www.irf.com ? 2013 international rectifier august 02, 2013 environmental qualifications qualification level industrial moisture sensitivity level 5mm x 6mm pqfn msl2 esd machine model (jesd22-a115a) class a <200v human body model (jesd22-a114f) class 1c ? 1000v to <2000v charged device model (jesd22-c101d) class iii ? 500v to 1000v rohs compliant yes data and specifications subject to change without notice. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com

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